This production technique is sometimes called the “stitching” technique; it consists in using, during a step of photolithographic exposure of an integrated circuit substrate, one and the same mask defining the pattern to be reproduced, which mask is shifted successively from one zone of the substrate to another adjacent zone, in the course of exposure sub-steps. The photolithography step consisting of this succession of sub-steps can be supplemented with other sub-steps of exposure of additional zones corresponding to different patterns, and therefore exposed through one or more different masks. The photolithography step is for example a step of defining a pattern of conductors in a conducting layer deposited on the substrate. Other photolithography steps are performed for the fabrication of the integrated circuit, and stitching, therefore repeated exposure of one and the same pattern in adjacent zones, will also be undertaken for each of them; this culminates, at the end of all the photolithography steps and at the end of the associated physical or chemical treatments, in an integrated circuit, certain mutually adjacent zones of which are strictly mutually identical.
In integrated circuits having a significant dimension of several centimetres by several centimetres and having to work at high operating speeds, a difficulty is encountered, namely the limited propagation speed of the signals; this limited speed gives rise to the risk that one and the same control signal, which must serve to control several identical circuits simultaneously, is transmitted with a non-zero time shift between the various identical zones. In particular, in the circuits which operate with a high-frequency clock, one and the same clock signal produced at one place in the integrated circuit may reach the various parts of the circuit at mutually shifted instants whereas these signals ought to arrive simultaneously for proper operation of the whole. For circuits of several centimetres by several centimetres, the shift may be several tens of nanoseconds, this being incompatible with operating rates of several tens of megahertz.
Document US 2008/201597 describes a memory system in which a clock signal propagates from one memory device to the next. This system comprises a memory interface including a circuit for compensating the propagation delays of the signals, based on the use of a tapped delay line and of multiplexers to select one from among the output signals of the said delay line.